Stephen King said, “Baseball is also a game of balance.” The pitcher and catcher must balance each other for a pitch to be on target. In a similar way, video players and displays must balance each other for a successful video presentation. In the baseball analogy, the video player is the pitcher, and the display is the catcher. The catcher sends a signal to the pitcher, the pitcher interprets the catcher’s signal for how to throw the ball, then the pitcher throws the pitch (sends the timing and resolution signals). If the pitcher misunderstands or does not follow the signal from the catcher, the pitch will not be on target (the video will not display properly).
In AV technology, each time a display (the catcher) connects to a video source, the video player (the pitcher) needs to determine and send the best output setting for the content that can be represented by the display; otherwise, you will not see the video on the display nor hear the audio from the display.
Before EDID was defined, there was no standard way for a video player to know the capabilities of the connected display. EDID is defined and published by VESA (Video Electronics Standards Association), and the most recent version is v1.4. The data format is defined as an upward-compatible 128-byte structure. v2.0 defines a new 256-byte structure, but this has been replaced by v1.3, which supports multiple extension blocks.
EDID information is stored in the display. When a display connects to a video player, the video player will retrieve the EDID from the display, also parsing the contents. The EDID might contain more than one 128-byte block. In practice, the video player will retrieve the first block, and based on information in this block, the video player will then decide how many additional blocks are provided by the display EDID. The first 128-byte EDID block is defined by VESA, which was initially used to define the capability of a DVI display. Another common EDID block is defined by CTA (Consumer Technology Association).
|Address in Decimal
|Data and description
|Fixed header: 00 FF FF FF FF FF FF 00
|EDID Structure Version/Revision
|Basic Display Parameters/Features
|Standard Timing Identification
|Detailed Timing Descriptions
The Display’s Video Timing is Key
Each bit in Established Timings represents common timing modes. If the display supports the specified video timing, the corresponding bit is set to 1; otherwise, the bit is set to 0.
Standard Timing Identification contains up to eight 2-byte fields. Each field describes the video vertical timing information and the image aspect ratio.
Detailed Timing Description contains up to four 18-byte fields. Each field describes detailed video timing information for the display descriptor.
Address 24 is the Feature Support bitmap table. Bit 1 represents the Preferred Timing Mode. If this bit is set to 1, the video player uses the first detailed timing block as the preferred video output information.
Besides EDID, VESA also publishes other standards, including the DMT (Display Monitor Timing) standard, the CVT (Coordinated Video Timings) standard, and the GTF (Generalized Timing Formula) standard. Download these standards for free from https://vesa.org/vesa-standards.
|CTA-861 block tag: 02
|Revision Number: 03
|Offset d where 18-byte Detailed Timing Descriptors
|Total number of Detailed Timing Descriptors and other information
|Lower 4 bits: Total number of Detailed Timing Descriptors
|Start of data block collection
|Start of 18-byte Detailed Timing Descriptors
|d + (18*n) ~ 126
CTA Data Block Collection includes VBD (Video Data Block) and other data blocks, and the VBD lists the video timing settings supported by the display. In the first byte of the VBD, bit 5–7 is set to 2 for identification, and bit 0–4 represents the total number of SVDs (Short Video Descriptors) that follow this byte.
Each SVD contains VIC (Video Identification Code) and each VIC represents a predefined video timing setting. When a VIC ranges from 1 to 64, bit 7 of the SVD is set to 1 to indicate that the display natively supports this format. VICs ranging from 128 to 192 are reserved. The player can distinguish if all bits in the SVD represent the VIC, or if the bits in the SVD represent the VIC in 1 though 64 but with the native bit set. The CTA-861 standard also lists a formula for how to extract VIC from SVD. The most recent version CTA-861 standard is CTA-861-G. For other free CTA standards, go to https://cta.tech/Resources/Standards.
Parsing EDID is an important task for each video player. Even information in a portion of the VESA or CTA might suggest the video timing. The video player decides the video timing output. In general, the video player will use the Preferred Timing in the EDID VESA block, but if the video player is a computer, it will use the maximum resolution in the EDID, and if the video player is a consumer device, it will use the maximum refresh rate it found in the EDID.
Computer-based video player behavior will be affected by the device driver the video player uses, when the resolution is lower than the output resolution from the computer UI. If a computer outputs 3840 x 2160 60 FPS, with a display that can accept this video input, if you select 1920 x 1080 60 FPS from the UI, the driver might decide to scale up the resolution, and still output in 3840 x 2160 60 FPS.
If a display shows the real input timing, it can also show the real video timing it received, and other equipment such as a video analyzer can get the real video timing and other information to help troubleshoot in the field.
In baseball, the pitcher and catcher must balance each other. As we have described here, the video player (similar to the pitcher) and the display (similar to the catcher) must also balance each other. Many factors influence the end result, such as the identification, timing, and resolution of the display. By following several VESA standards, including EDID (Extended Display Identification Data), DMT (Display Monitor Timing), CVT (Coordinated Video Timings), and GTF (Generalized Timing Formula) standards, video players can project flawless video presentations on end-user displays.
Aries Chuang has more than 25+ years of programming experience, as a product engineer, his primary focus are audio, video and networking, also provide firmware and software customize design for Black Box products.